The use of a clock (or reference) signal is common in any electronic system. Further, in more advanced electronic systems, such as communication systems using multiple antennas or antenna arrays, for example, clock signals of the same frequency but with different phases (or multiphase clock signals) are required.
There are conventional methods available for generating multiphase clock signals.
A first conventional method to generate multiphase clock signals would be to use a plurality of phase lock loop circuits. As used herein, the term plurality refers to two or more. In this context, a plurality of phase lock loop circuits means two or more phase lock loop (PLL) circuits.
A second conventional method to generate multiphase clock signals would be to use a plurality of delay lock loop (DLL) circuits. It can be seen that the second conventional method may be derived from the first conventional method by merely replacing the PLL circuits used with DLL circuits.
A third conventional method to generate multiphase clock signals would be to use a plurality of phase interpolator circuits. In this conventional method, a first phase delayed clock signal may be generated based on an input clock signal. Subsequently, the plurality of phase interpolator circuits may be used to generate further a plurality of phase delayed clock signals based on the input clock signal and the first phase delayed clock signal.
In this document, an alternative method of generating multiphase clock signals is provided.